The present invention relates generally to integrated circuits, and, more particularly, to a voltage monitoring circuit for an integrated circuit.
Integrated circuits (IC) include various analog and digital circuits such as operational amplifiers, voltage regulators, power management controllers (PMC), sensors, logic circuits, and non-volatile memories. The voltage regulators generate and provide supply voltage signals to the analog and digital circuits while the PMCs monitor the supply voltage signals. A PMC includes voltage monitoring circuits such as high and low voltage detectors (HVD and LVD). The HVDs and LVDs insure that changes in voltage levels of the supply voltage signals beyond defined operating limits are detected in order to prevent damage to the IC caused by out of specification voltages.
FIG. 1 shows an IC 100 that includes a voltage regulator 102 for generating a supply voltage signal and a power management controller (PMC) 104. The PMC 104 includes a reference voltage generator 106 and a voltage monitoring circuit 108. The voltage monitoring circuit 108 includes a switching circuit 110 and a comparator 112. The switching circuit 110 includes a first switch 114 and a second switch 116. In this example, the voltage monitoring circuit 108 is a low-voltage detector (LVD) 108.
The reference voltage generator 106 generates an LVD reference voltage signal (not shown) that toggles between a low LVD reference voltage signal (hereinafter a “first reference voltage signal”) and a high LVD reference voltage signal (hereinafter a “second reference voltage signal”), where the first reference voltage signal is less than the second reference voltage signal.
The switches 114 and 116 each have a first input terminal connected to the reference voltage generator 106 for receiving the reference voltage signals.
The comparator 112 has a first input terminal connected to the voltage regulator 102 for receiving the supply voltage signal, a second input terminal connected to the switches 116 and 114 for receiving one of the first and second reference voltage signals, and an output terminal for outputting a voltage monitor signal. The switches 114 and 116 each have a second input terminal connected to the output terminal of the voltage comparator circuit 112 for receiving the voltage monitor signal. The second input terminal of the switch 114 is an low active input terminal. The LVD reference voltage signal toggles between the first and second reference voltage signals based on the voltage monitor signal.
In operation, when the IC 100 is powered up, a power-on-reset (POR) generator (not shown) initializes the voltage monitor signal to a logic low state. The switch 114 receives the low voltage monitor signal, switches on, and outputs the second reference voltage signal. The switch 116 receives the low voltage monitor signal, and switches off. The comparator 112 compares the supply voltage signal with the second reference voltage signal.
When the supply voltage signal is less than the second reference voltage signal, the comparator 112 generates the voltage monitor signal at a logic low state. The switch 114 receives the low voltage monitor signal and continues to output the second reference voltage signal. When the supply voltage signal exceeds the second reference voltage signal, the comparator 112 generates a high voltage monitor signal. The switch 114 receives the high voltage monitor signal and switches off, while the switch 116 receives the high voltage monitor signal, switches on, and outputs the first reference voltage signal.
The comparator 112 compares the supply voltage signal with the first reference voltage signal. When the supply voltage signal is greater than the first reference voltage signal, the comparator 112 outputs the voltage monitor signal at a logic high state. When the supply voltage signal is less than the first reference voltage signal, the comparator 112 outputs the voltage monitor signal at a logic low state. Thus, the LVD reference voltage signal toggles between the first and second reference voltage signals based on the logic state of the voltage monitor signal.
When the IC 100 is powered on, various circuits (not shown) within the IC are reset, i.e., set to corresponding predefined states. A predefined state refers to a known and a stable state. To facilitate the reset of the circuits, the IC 100 further includes a reset controller (not shown). The POR generator generates a POR signal (not shown) to initiate a reset sequence. During the reset sequence, the reset controller initializes the circuits to corresponding predefined states.
Generally, the reset sequence includes multiple reset phases. For example, the IC 100 may have four reset phases (first through fourth). In the first reset or POR phase, circuits such as the voltage regulator 102 and the PMC 104 are initialized. The IC 100 transitions to a second reset phase from the first reset phase during which a clock signal is initialized, i.e., the IC 100 receives a predefined minimum number of clock cycles of the clock signal from a clock generator (not shown). Subsequently, the IC 100 transitions from the second reset phase to a third reset phase. In the third reset phase, a non-volatile memory such as a flash memory (not shown) is initialized. Further, configuration information such as factory settings and boot code in the non-volatile memory are accessed by the reset controller during the third reset phase. Next, the IC 100 transitions to a fourth reset phase during which the circuits perform self-tests and a few of the circuits fetch configuration settings from the non-volatile memory.
FIG. 2 is a timing diagram that illustrates the LVD reference voltage signal, a trimming code, the voltage monitor signal, a reset signal, and the reset phases of the IC 100. At power up (time period t0 to t2), the POR generator initializes the voltage monitor signal at a logic low state. The switch 114 receives the low voltage monitor signal, switches on, and outputs the second reference voltage signal. The voltage comparator circuit 112 compares the supply voltage signal with the second reference voltage signal. However, the supply voltage signal has a slow ramp rate, i.e., the voltage level of the supply voltage signal increases until a desired voltage level at a slow rate during the reset sequence (time period t0 to t16) is achieved.
During power up and the first reset phase (time period t0 to t4), the voltage level of the supply voltage signal is less than the voltage level of the second reference voltage signal. Thus, the voltage monitor signal generated by the voltage comparator circuit 112 is at a logic low state (time period t0 to t4).
At time t4, the voltage level of the supply voltage signal exceeds the voltage level of the second reference voltage signal and the voltage monitor signal toggles from low to high. During the second and third reset phases (time period t4 to t8) the voltage monitor signal is high and the LVD reference voltage signal toggles from the second reference voltage signal to the first reference voltage signal.
In the fourth reset phase, at time t9, the reset controller loads the trimming code into the reference voltage generator 106. As a result, the LVD reference voltage signal is trimmed at time t10. After the LVD reference voltage signal is trimmed, the LVD reference voltage signal toggles between trimmed first and second reference voltage signals based on the logic state of the voltage monitor signal. Thus, during time period t10 to t15, the voltage level of the supply voltage signal is substantially less than a voltage level of the trimmed first reference voltage signal. However, as the supply voltage signal has a slow ramp rate, the voltage level of the supply voltage signal remains substantially equal to the voltage level of the trimmed first reference voltage signal during time period t10 to t15. When a difference between the voltage levels of the supply voltage signal and the trimmed first reference voltage signal decreases (e.g. less than 10 millivolts), a response time of the voltage comparator circuit 112 increases. The response time of the voltage comparator circuit 112 is defined as the time required by the voltage comparator circuit 112 to change the logic state of the voltage monitor signal when the voltage levels of the supply voltage signal and the LVD reference voltage signal change. Such an increase in the response time of the voltage comparator circuit 112 is known as meta-stability. Thus, the voltage monitor signal fails to go low during time period t10 to t15 due to meta-stability.
Although the voltage level of the supply voltage signal is less than the voltage level of the trimmed first reference voltage signal, the voltage monitor signal generated by the voltage comparator circuit 112 stays high from time period t10 to t15. When the IC 100 is in the fourth reset phase, the logic high voltage monitor signal indicates that the voltage level of the supply voltage signal is greater than the voltage level of the trimmed first reference voltage signal. Thus, the reset controller receives the logic high voltage monitor signal and generates a high reset signal (time t13). The IC 100 exits the fourth reset phase and transitions to a run mode of operation (time period t13 to t15). This transition to the run mode at time t13 is referred to as a false reset de-assertion. At time t15, the voltage monitor signal goes low because the voltage level of the supply voltage signal is less than the voltage level of the trimmed first reference voltage signal. As a result, the reset signal generated by the reset controller is low and the IC 100 transitions back to the first reset phase. The IC 100 transitions through the reset phases of the reset sequence to the run mode of operation again. However, due to the slow ramp rate of the supply voltage signal, the voltage level of the supply voltage signal may be less than the voltage level of the trimmed first reference voltage signal (time t10). This results in an increase in the response time of the voltage comparator circuit 112 and hence, results in the IC 100 having multiple false reset de-assertions.
Various processes such as fetching and execution of code begins in the run mode. Such processes are interrupted when the IC 100 transitions back to the first reset phase and may result in loss of data packets. Further, when the IC 100 communicates with an external IC (not shown), the false reset de-assertion may result in a loss of data packets during the communication with the external IC. When the IC 100 is used in a display application, the false reset de-assertions cause the display to flicker. Moreover, to avoid damage to the IC 100 due to such multiple false reset de-assertions, the IC 100 may be permanently held in reset by a supervisory circuit, which in turn limits the availability of IC 100 for safety critical applications.
One way to overcome meta-stability uses a counter to gate the fourth reset phase of the IC 100 for a predetermined time. The predetermined time corresponds to the known worst case response time of the voltage comparator circuit 112 during the meta-stability condition. However, the response time of the voltage comparator circuit 112 is not deterministic. For example, if the meta-stability condition is overcome before the predetermined time period ends, there will be a loss of operational time of the IC 100, thereby ineffectively extending the time for which the IC 100 is in the reset phase. In another example, the meta-stability condition is not overcome even after the predetermined time period has lapsed. Thus, the counter may not efficiently gate the fourth reset phase and overcome meta-stability.
Therefore, it would be advantageous to have a voltage monitoring circuit in an IC that efficiently overcomes the meta-stability condition of the voltage monitoring circuit, and does not cause false reset de-assertions of the IC.